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1 2270f ltc2270 typical application features applications description 16-bit, 20msps low noise dual adc n low power instrumentation n software defined radios n portable medical imaging n multi-channel data acquisition n two-channel simultaneously sampling adc n 84.1db snr (46v rms input referred noise) n 99db sfdr n 2.3lsb inl(max) n low power: 160mw total, 80mw per channel n single 1.8v supply n cmos, ddr cmos, or ddr lvds outputs n selectable input ranges: 1v p-p to 2.1v p-p n 200mhz full power bandwidth s/h n shutdown and nap modes n serial spi port for configuration n pin compatible with ltc2180: 16-bit, 25msps, 78mw ltc2140-14: 14-bit, 25msps, 50mw n 64-lead (9mm 9mm) qfn package the ltc ? 2270 is a two-channel simultaneous sampling 16-bit a/d converter designed for digitizing high frequency, wide dynamic range signals. it is perfect for demanding applications with ac performance that includes 84.1db snr and 99db spurious free dynamic range (sfdr). dc specs include 1lsb inl (typ), 0.2lsb dnl (typ) and no missing codes over temperature. the transition noise is 1.44lsb rms . the digital outputs can be either full rate cmos, double data rate cmos, or double data rate lvds. a separate output power supply allows the cmos output swing to range from 1.2v to 1.8v. the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. integral non-linearity (inl) cmos, ddr cmos or ddr lvds outputs 1.8v v dd 1.8v ov dd clock control d1_15 d1_0 2270 ta01 ch 1 analog input output drivers t t t gnd ognd s/h 16-bit adc core ch 2 analog input s/h 16-bit adc core d2_15 d2_0 t t t 20mhz clock output code 0 C2.0 C1.5 C1.0 inl error (lsb) C0.5 0.5 0.0 1.0 1.5 2.0 16384 32768 49152 65536 2270 ta02
ltc2270 2 2270f absolute maximum ratings supply voltages (v dd , ov dd ) ....................... C0.3v to 2v analog input voltage (a in + , a in C , par/ ser , sense) (note 3) .......... C0.3v to (v dd + 0.2v) digital input voltage (enc + , enc C , cs , sdi, sck) (note 4) .................................... C0.3v to 3.9v sdo (note 4) ............................................. C0.3v to 3.9v (notes 1, 2) pin configurations digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range ltc2270c ................................................ 0c to 70c ltc2270i ............................................. C40c to 85c storage temperature range .................. C65c to 150c full-rate cmos output mode double data rate cmos output mode top view up package 64-lead (9mm s 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_5 47 d1_4 46 d1_3 45 d1_2 44 d1_1 43 d1_0 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_15 37 d2_14 36 d2_13 35 d2_12 34 d2_11 33 d2_10 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of1 59 of2 58 d1_15 57 d1_14 56 d1_13 55 d1_12 54 d1_11 53 d1_10 52 d1_9 51 d1_8 50 d1_7 49 d1_6 v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 d2_0 23 d2_1 24 d2_2 25 d2_3 26 d2_4 27 d2_5 28 d2_6 29 d2_7 30 d2_8 31 d2_9 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb top view up package 64-lead (9mm s 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_4_5 47 dnc 46 d1_2_3 45 dnc 44 d1_0_1 43 dnc 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_14_15 37 dnc 36 d2_12_13 35 dnc 34 d2_10_11 33 dnc 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of2_1 59 dnc 58 d1_14_15 57 dnc 56 d1_12_13 55 dnc 54 d1_10_11 53 dnc 52 d1_8_9 51 dnc 50 d1_6_7 49 dnc v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 dnc 23 d2_0_1 24 dnc 25 d2_2_3 26 dnc 27 d2_4_5 28 dnc 29 d2_6_7 30 dnc 31 d2_8_9 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb 3 2270f ltc2270 order information lead free finish tape and reel part marking* package description temperature range ltc2270cup#pbf ltc2270cup#trpbf ltc2270up 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2270iup#pbf ltc2270iup#trpbf ltc2270up 64-lead (9mm 9mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ double data rate lvds output mode top view up package 64-lead (9mm s 9mm) plastic qfn v dd 1 v cm1 2 gnd 3 a in1 + 4 a in1 C 5 gnd 6 refh 7 refl 8 refh 9 refl 10 par/ ser 11 a in2 + 12 a in2 C 13 gnd 14 v cm2 15 v dd 16 48 d1_4_5 + 47 d1_4_5 C 46 d1_2_3 + 45 d1_2_3 C 44 d1_0_1 + 43 d1_0_1 C 42 ov dd 41 ognd 40 clkout + 39 clkout C 38 d2_14_15 + 37 d2_14_15 C 36 d2_12_13 + 35 d2_12_13 C 34 d2_10_11 + 33 d2_10_11 C 65 gnd 64 v dd 63 sense 62 v ref 61 sdo 60 of2_1 + 59 of2_1 C 58 d1_14_15 + 57 d1_14_15 C 56 d1_12_13 + 55 d1_12_13 C 54 d1_10_11 + 53 d1_10_11 C 52 d1_8_9 + 51 d1_8_9 C 50 d1_6_7 + 49 d1_6_7 C v dd 17 enc + 18 enc C 19 cs 20 sck 21 sdi 22 d2_0_1 C 23 d2_0_1 + 24 d2_2_3 C 25 d2_2_3 + 26 d2_4_5 C 27 d2_4_5 + 28 d2_6_7 C 29 d2_6_7 + 30 d2_8_9 C 31 d2_8_9 + 32 t jmax = 150c, ja = 20c/w exposed pad (pin 65) is gnd, must be soldered to pcb pin configurations ltc2270 4 2270f analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2.1 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l 0.65 v cm v cm + 200mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 20msps 32 a i in1 analog input leakage current (no encode) 0 < a in + , a in C < v dd l C1 1 a i in2 par/ ser input leakage current 0 < par/ ser < v dd l C1 1 a i in3 sense input leakage current 0.625 < sense < 1.3v l C2 2 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter single-ended encode differential encode 85 100 fs rms fs rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 5 test circuit 200 mhz converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units resolution (no missing codes) l 16 bits integral linearity error differential analog input (note 6) l C2.3 1 2.3 lsb differential linearity error differential analog input l C0.8 0.2 0.8 lsb offset error (note 7) l C7 1.3 7 mv gain error internal reference external reference l C1.6 1.2 C0.3 1 %fs %fs offset drift 10 v/c full-scale drift internal reference external reference 30 10 ppm/c ppm/c gain matching l C0.2 0.06 0.2 %fs offset matching l C10 1.5 10 mv transition noise 1.44 lsb rms 5 2270f ltc2270 internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 l 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/c v cm output resistance C600a < i out < 1ma 4 v ref output voltage i out = 0 l 1.230 1.250 1.270 v v ref output temperature drift 25 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions min typ max units snr signal-to-noise ratio 1.4mhz input 5mhz input 30mhz input 70mhz input l 82.3 84.1 84.1 83.8 82.7 dbfs dbfs dbfs dbfs sfdr spurious free dynamic range, 2nd harmonic 1.4mhz input 5mhz input 30mhz input 70mhz input l 90 99 98 98 90 dbfs dbfs dbfs dbfs spurious free dynamic range, 3rd harmonic 1.4mhz input 5mhz input 30mhz input 70mhz input l 92 99 98 98 96 dbfs dbfs dbfs dbfs spurious free dynamic range, 4th harmonic or higher 1.4mhz input 5mhz input 30mhz input 70mhz input l 95 110 110 105 100 dbfs dbfs dbfs dbfs s/(n+d) signal-to-noise plus distortion ratio 1.4mhz input 5mhz input 30mhz input 70mhz input l 81.9 83.9 83.9 83.7 82.0 dbfs dbfs dbfs dbfs crosstalk 10mhz input C110 dbc ltc2270 6 2270f digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) differential encode mode (enc C not tied to gnd) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance (note 8) 3.5 pf single-ended encode mode (enc C tied to gnd) v ih high level input voltage v dd = 1.8v l 1.2 v v il low level input voltage v dd = 1.8v l 0.6 v v in input voltage range enc + to gnd l 0 3.6 v r in input resistance (see figure 11) 30 k c in input capacitance (note 8) 3.5 pf digital inputs ( cs, sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 3 pf digital data outputs (cmos modes: full data rate and double data rate) ov dd = 1.8v v oh high level output voltage i o = C500a l 1.750 1.790 v v ol low level output voltage i o = 500a l 0.010 0.050 v ov dd = 1.5v v oh high level output voltage i o = C500a 1.488 v v ol low level output voltage i o = 500a 0.010 v ov dd = 1.2v v oh high level output voltage i o = C500a 1.185 v v ol low level output voltage i o = 500a 0.010 v digital data outputs (lvds mode) v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 247 350 175 454 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l 1.125 1.250 1.250 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 7 2270f ltc2270 power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 9) symbol parameter conditions min typ max units cmos output modes: full data rate and double data rate v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.1 1.8 1.9 v i vdd analog supply current dc input sine wave input l 89 89.5 100 ma ma i ovdd digital supply current sine wave input, ov dd = 1.2v 2 ma p diss power dissipation dc input sine wave input, ov dd = 1.2v l 160 164 180 mw mw lvds output mode v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 v i vdd analog supply current sine input, 1.75ma mode sine input, 3.5ma mode l 91 93 105 ma ma i ovdd digital supply current (0v dd = 1.8v) sine input, 1.75ma mode sine input, 3.5ma mode l 38 73 82 ma ma p diss power dissipation sine input, 1.75ma mode sine input, 3.5ma mode l 232 299 337 mw mw all output modes p sleep sleep mode power 0.5 mw p nap nap mode power 12 mw p diffclk power increase with differential encode mode enabled (no increase for nap or sleep modes) 20 mw timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units f s sampling frequency (note 10) l 1 20 mhz t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 23.5 2 25 25 500 500 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 23.5 2 25 25 500 500 ns ns t ap sample-and-hold acquisition delay time 0 ns symbol parameter conditions min typ max units digital data outputs (cmos modes: full data rate and double data rate) t d enc to data delay c l = 5pf (note 8) l 1.1 1.7 3.1 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.4 2.6 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency full data rate mode double data rate mode 6 6.5 6 6.5 cycles cycles ltc2270 8 2270f symbol parameter conditions min typ max units digital data outputs (lvds mode) t d enc to data delay c l = 5pf (note 8) l 1.1 1.8 3.2 ns t c enc to clkout delay c l = 5pf (note 8) l 1 1.5 2.7 ns t skew data to clkout skew t d C t c (note 8) l 0 0.3 0.6 ns pipeline latency 6.5 6.5 cycles spi port timing (note 8) t sck sck period write mode readback mode, c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5n s t h sck to cs setup time l 5n s t ds sdi setup time l 5n s t dh sdi hold time l 5n s t do sck falling to sdo valid readback mode, c sdo = 20pf, r pullup = 2k l 125 ns timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 20mhz, lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2.1v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = 1.8v, f sample = 20mhz, cmos outputs, enc + = single-ended 1.8v square wave, enc C = 0v, input range = 2.1v p-p with differential drive, 5pf load on each digital output unless otherwise noted. the supply current and power dissipation specifications are totals for the entire ic, not per channel. note 10: recommended operating conditions. 9 2270f ltc2270 typical performance characteristics integral non-linearity (inl) differential non-linearity (dnl) 64k point fft, f in = 1.4mhz, C1dbfs, 20msps output code 0 C2.0 C1.5 C1.0 inl error (lsb) C0.5 0.5 0.0 1.0 1.5 2.0 16384 32768 49152 65536 2270 g01 output code C1.0 C0.4 C0.2 C0.6 C0.8 dnl error (lsb) 0.0 0.4 0.2 0.6 0.8 1.0 2270 g02 0 16384 32768 49152 65536 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 0 C20 2270 g03 0 2 6 410 8 64k point fft, f in = 5.1mhz, C1dbfs, 20msps 64k point fft, f in = 10.1mhz, C1dbfs, 20msps 64k point fft, f in = 30.3mhz, C1dbfs, 20msps 64k point fft, f in = 70.3mhz, C1dbfs, 20msps 64k point 2-tone fft, f in = 14.8, 15.2mhz, C7dbfs, 20msps frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 C20 0 2270 g04 024 6 810 frequency (mhz) C100 C140 C120 C60 C80 amplitude (dbfs) C40 C20 0 2270 g05 0 2 86 41 0 frequency (mhz) C100 C120 C140 C60 C80 amplitude (dbfs) C40 C20 0 2270 g06 0 2 6 410 8 frequency (mhz) 0 C120 C140 C80 C100 amplitude (dbfs) C60 0 C20 C40 246810 2270 g08 output code n-6 10000 5000 0 40000 35000 30000 25000 20000 15000 count n-5 n-4 n-3 n-2 n-1 n+6 n+5 n+4 n+3 n+2 n+1 n 2270 g09 shorted input histogram frequency (mhz) 0 C100 C120 C140 C60 C80 amplitude (dbfs) C40 C20 0 2 6 410 8 2270 g07 ltc2270 10 2270f typical performance characteristics sfdr vs input level, f in = 5mhz, 20msps, 2.1v range input frequency (mhz) 0 85 80 75 70 90 2nd and 3rd harmonic (dbfs) 95 105 100 20 40 60 80 100 120 140 2270 g12 2nd 3rd input level (dbfs) C80 40 60 50 80 70 130 120 110 100 90 sfdr (dbc and dbfs) C70 C40C50C60 0C10C20C30 2270 g13 dbfs dbc 0 20 40 60 80 100 120 140 input frequency (mhz) 83 82 81 80 79 85 84 snr (dbfs) 2270 g10 single-ended encode differential encode snr vs input frequency, C1dbfs, 20msps, 2.1v range i vdd vs sample rate, 5mhz, C1dbfs sine wave input on each channel i ovdd vs sample rate, 5mhz, C1dbfs sine wave input on each channel snr, sfdr vs sample rate, f in = 5mhz, C1dbfs sfdr vs analog input common mode, f in = 9.7mhz, 20msps, 2.1v range snr vs sense, f in = 5mhz, C1dbfs sample rate (msps) 0 80 70 90 100 i vdd (ma) 5 101520 2270 g14 3.5ma lvds outputs cmos outputs sample rate (msps) 0 10 0 20 30 80 70 60 50 40 i ovdd (ma) 5 101520 2270 g15 3.5ma lvds 1.75ma lvds 1.8v cmos sense pin (v) 0.6 77 78 79 80 snr (dbfs) 81 82 85 84 83 0.80.7 1 1.21.1 0.9 1.3 2270 g16 80 85 sfdr (dbfs) 90 95 100 2270 g17 input common mode (v) 0.6 0.80.7 0.9 1.11 1.2 v dd 1.9v v dd 1.7v sample rate (msps) 0 80 90 snr, sfdr (dbfs) 100 110 10 51520 2270 g18 sfdr snr 020 60 40 80 100 120 140 input frequency (mhz) 95 90 85 80 75 70 105 100 2nd and 3rd harmonic (dbfs) 2270 g11 2nd 3rd 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 2.1v range 2nd, 3rd harmonic vs input frequency, C1dbfs, 20msps, 1.05v range 11 2270f ltc2270 pins that are the same for all digital output modes v dd (pins 1, 16, 17, 64): analog power supply, 1.7v to 1.9v. bypass to ground with 0.1f ceramic capacitors. adjacent pins can share a bypass capacitor. v cm1 (pin 2): common mode bias output, nominally equal to v dd /2. v cm1 should be used to bias the common mode of the analog inputs to channel 1. bypass to ground with a 1f ceramic capacitor. gnd (pins 3, 6, 14): adc power ground. a in1 + (pin 4): channel 1 positive differential analog input. a in1 C (pin 5): channel 1 negative differential analog input. refh (pins 7, 9): adc high reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. refl (pins 8, 10): adc low reference. see the applica- tions information section for recommended bypassing circuits for refh and refl. par/ ser (pin 11): programming mode selection pin. con- nect to ground to enable the serial programming mode. cs , sck, sdi, sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs, sck, sdi, sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or v dd and not be driven by a logic signal. a in2 + (pin 12): channel 2 positive differential analog input. a in2 C (pin 13): channel 2 negative differential analog input. v cm2 (pin 15): common mode bias output, nominally equal to v dd /2. v cm2 should be used to bias the common mode of the analog inputs to channel 2. bypass to ground with a 1f ceramic capacitor. enc + (pin 18): encode input. conversion starts on the rising edge. enc C (pin 19): encode complement input. conversion starts on the falling edge. tie to gnd for single-ended encode mode. cs (pin 20): in serial programming mode, (par/ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs controls the clock duty cycle stabilizer (see table 2). cs can be driven with 1.8v to 3.3v logic. sck (pin 21): in serial programming mode, (par/ser = 0v), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck controls the digital output mode. (see table 2). sck can be driven with 1.8v to 3.3v logic. sdi (pin 22): in serial programming mode, (par/ser = 0v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode (par/ ser = v dd ), sdi can be used together with sdo to power down the part (see table 2). sdi can be driven with 1.8v to 3.3v logic. ognd (pin 41): output driver ground. must be shorted to the ground plane by a very low inductance path. use multiple vias close to the pin. ov dd (pin 42): output driver supply. bypass to ground with a 0.1f ceramic capacitor. sdo (pin 61): in serial programming mode, (par/ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control regis- ters and can be latched on the falling edge of sck. sdo is an open-drain nmos output that requires an external 2k pull-up resistor to 1.8v C 3.3v. if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in the parallel programming mode (par/ ser = v dd ), sdo can be used together with sdi to power down the part (see table 2). when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. pin functions ltc2270 12 2270f pin functions v ref (pin 62): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. the output voltage is nominally 1.25v. sense (pin 63): reference programming pin. connecting sense to v dd selects the internal reference and a 1.05v input range. connecting sense to ground selects the internal reference and a 0.525v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.84 ? v sense . ground (exposed pad pin 65): the exposed pad must be soldered to the pcb ground. full-rate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d2_0 to d2_15 (pins 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38): channel 2 digital outputs. d2_15 is the msb. clkout C (pin 39): inverted version of clkout + . clkout + (pin 40): data output clock. the digital outputs normally transition at the same time as the falling edge of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d1_0 to d1_15 (pins 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58): channel 1 digital outputs. d1_15 is the msb. of2 (pin 59): channel 2 over/under flow digital output. of2 is high when an overflow or underflow has occurred. of1 (pin 60): channel 1 over/under flow digital output. of1 is high when an overflow or underflow has occurred. double data rate cmos output mode all pins below have cmos output levels (ognd to ov dd ) d2_0_1 to d2_14_15 (pins 24, 26, 28, 30, 32, 34, 36, 38): channel 2 double data rate digital outputs. two data bits are multiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. dnc (pins 23, 25, 27, 29, 31, 33, 35, 37, 43, 45, 47, 49, 51, 53, 55, 57, 59): do not connect these pins. clkout C (pin 39): inverted version of clkout + . clkout + (pin 40): data output clock. the digital outputs normally transition at the same time as the falling and ris- ing edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d1_0_1 to d1_14_15 (pins 44, 46, 48, 50, 52, 54, 56, 58): channel 1 double data rate digital outputs. two data bits are multiplexed onto each output pin. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. of2_1 (pin 60): over/under flow digital output. of2_1 is high when an overflow or underflow has occurred. the over/under flow for both channels are multiplexed onto this pin. channel 2 appears when clkout + is low, and channel 1 appears when clkout + is high. 13 2270f ltc2270 double data rate lvds output mode all pins below have lvds output levels. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. d2_0_1 C /d2_0_1 + to d2_14_15 C /d2_14_15 + (pins 23/24, 25/26, 27/28, 29/30, 31/32, 33/34, 35/36, 37/38): chan- nel 2 double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. clkout C /clkout + (pins 39/40): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. d1_0_1 C /d1_0_1 + to d1_14_15 C /d1_14_15 + (pins 43/44, 45/46, 47/48, 49/50, 51/52, 53/54, 55/56, 57/58): chan- nel 1 double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (d0, d2, d4, d6, d8, d10, d12, d14) appear when clkout + is low. the odd data bits (d1, d3, d5, d7, d9, d11, d13, d15) appear when clkout + is high. of2_1 C /of2_1 + (pins 59/60): over/under flow digital output. of2_1 + is high when an overflow or underflow has occurred. the over/under flow for both channels are multiplexed onto this pin. channel 2 appears when clkout + is low, and channel 1 appears when clkout + is high. pin functions ltc2270 14 2270f functional block diagram diff ref amp ref buf 2.2f 1f 1f internal clock signals refh refl clock/duty cycle control range select 1.25v reference enc + refh refl enc C correction logic sdo cs ognd of1 ov dd d1_15 clkout C clkout + d1_0 2270 f01 sense v ref ch 1 analog input 2.2f v cm1 1f v dd /2 output drivers mode control registers sck par/ ser sdi t t t gnd s/h 16-bit adc core ch 2 analog input s/h 16-bit adc core v cm2 1f of2 d2_15 d2_0 t t t v dd figure 1. functional block diagram 15 2270f ltc2270 full-rate cmos output mode timing all outputs are single-ended and have cmos levels timing diagrams t h t d t c t l b C 6 b C 5 b C 4 b C 3 b C 2 t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input enc C enc + clkout + clkout C d2_0 - d2_15, of2 t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input a C 6 a C 5 a C 4 a C 3 a C 2 d1_0 - d1_15, of1 2270 td01 ltc2270 16 2270f timing diagrams double data rate cmos output mode timing all outputs are single-ended and have cmos levels t d t t t t d t c t c t l bit 0 a-6 bit 1 a-6 bit 0 a-5 bit 1 a-5 bit 0 a-4 bit 1 a-4 bit 0 a-3 bit 1 a-3 bit 0 a-2 bit 14 a-6 bit 15 a-6 bit 14 a-5 bit 15 a-5 bit 14 a-4 bit 15 a-4 bit 14 a-3 bit 15 a-3 bit 14 a-2 enc C enc + d1_0_1 d1_14_15 t t t bit 0 b-6 bit 1 b-6 bit 0 b-5 bit 1 b-5 bit 0 b-4 bit 1 b-4 bit 0 b-3 bit 1 b-3 bit 0 b-2 bit 14 b-6 bit 15 b-6 bit 14 b-5 bit 15 b-5 bit 14 b-4 bit 15 b-4 bit 14 b-3 bit 15 b-3 bit 14 b-2 of b-6 of a-6 of b-5 of a-5 of b-4 of a-4 of b-3 of a-3 of b-2 d2_0_1 d2_14_15 clkout + clkout C of2_1 2270 td02 t h t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input 17 2270f ltc2270 timing diagrams double data rate lvds output mode timing all outputs are differential and have lvds levels t d t t t t d t c t c t l bit 0 a-6 bit 1 a-6 bit 0 a-5 bit 1 a-5 bit 0 a-4 bit 1 a-4 bit 0 a-3 bit 1 a-3 bit 0 a-2 bit 14 a-6 bit 15 a-6 bit 14 a-5 bit 15 a-5 bit 14 a-4 bit 15 a-4 bit 14 a-3 bit 15 a-3 bit 14 a-2 enc C enc + d1_0_1 + d1_14_15 + t t t bit 0 b-6 bit 1 b-6 bit 0 b-5 bit 1 b-5 bit 0 b-4 bit 1 b-4 bit 0 b-3 bit 1 b-3 bit 0 b-2 bit 14 b-6 bit 15 b-6 bit 14 b-5 bit 15 b-5 bit 14 b-4 bit 15 b-4 bit 14 b-3 bit 15 b-3 bit 14 b-2 of b-6 of a-6 of b-5 of a-5 of b-4 of a-4 of b-3 of a-3 of b-2 d2_0_1 + d2_14_15 + clkout + clkout C of2_1 + d1_0_1 C d1_14_15 C d2_0_1 C d2_14_15 C of2_1 C 2270 td03 t h t ap a + 1 a + 2 a + 4 a + 3 a ch 1 analog input t ap b + 1 b + 2 b + 4 b + 3 b ch 2 analog input ltc2270 18 2270f a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 2270 td04 cs sck sdi r/w sdo high impedance timing diagrams 19 2270f ltc2270 converter operation the ltc2270 is a low power, two-channel, 16-bit, 20msps a/d converter that is powered by a single 1.8v supply. the analog inputs must be driven differentially. the encode input can be driven differentially, or single ended for lower power consumption. the digital outputs can be cmos, double data rate cmos (to halve the number of output lines), or double data rate lvds (to reduce digital noise in the system.) many additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differen- tially around a common mode voltage set by the v cm1 or v cm2 output pins, which are nominally v dd /2. for the 2.1v input range, the inputs should swing from v cm C 525mv to v cm + 525mv. there should be 180 phase difference between the inputs. the two channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc component values should be chosen based on the applications input frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figure 4 to figure 5) has better balance, resulting in lower a/d distortion. c sample 17pf r on 24 r on 24 v dd v dd ltc2270 a in + 2270 f02 c sample 17pf v dd a in C enc C enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 25 25 25 25 50 0.1f a in + a in C 12pf 1f v cm ltc2270 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 2270 f03 figure 2. equivalent input circuit. only one of the two analog channels is shown figure 3. analog input circuit using a transformer. recommended for input frequencies from 1mhz to 40mhz applications information ltc2270 20 2270f applications information figure 5. recommended front-end circuit for input frequencies above 80mhz amplifier circuits figure 6 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac-coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. if dc coupling is necessary, use a differential amplifier with an output common mode set by the ltc2270 v cm pin (figure 7). figure 4. recommended front-end circuit for input frequencies from 5mhz to 80mhz reference the ltc2270 has an internal 1.25v voltage reference. for a 2.1v input range using the internal reference, connect sense to v dd . for a 1.05v input range using the internal reference, connect sense to ground. for a 2.1v input range with an external reference, apply a 1.25v reference voltage to sense (figure 9). the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v. the input range will then be 1.68 ? v sense . the v ref , refh and refl pins should be bypassed as shown in figure 8. a low inductance 2.2f interdigitated capacitor is recommended for the bypass between refh and refl. this type of capacitor is available at a low cost from multiple suppliers. 25 12 12 25 50 0.1f a in + a in C 8.2pf 1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2270 f04 ltc2270 25 25 50 0.1f a in + a in C 1.8pf 1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1tl resistors, capacitors are 0402 package size 2270 f05 ltc2270 25 25 200 200 0.1f a in + a in C 1f 12pf 12pf v cm ltc2270 2270 f06 C C + + analog input high speed differential amplifier 0.1f 25 25 a in + a in C 1f 25pf 25pf v cm ltc2270 2270 f07 C + + C analog input cm figure 6. front-end circuit using a high speed differential amplifier figure 7. dc-coupled amplifier 21 2270f ltc2270 applications information v ref refh refh sense c1 tie to v dd for 2.1v range; tie to gnd for 1.05v range; 3 " / ( & |